There can be errors in data transfers between host and memory devices. These link errors may be detected and often corrected by incorporating error correction codes (ECC) in data transfers. Two techniques have been conventionally used to implement ECC. In the first conventional technique, the input/output (I/O) width is increased to accommodate both the data and the ECC. In the second conventional technique, the ECC bits are transferred between the host and the memory by extending the data burst length.
In the first conventional technique, conventional server and computing systems typically use 72-bit I/O width memory module (64-bit data and corresponding 8-bit ECC) to enhance reliability of memory link and memory cell array. FIG. 1 illustrates a simplified diagram of a conventional memory subsystem 100 which includes a host system-on-chip (SOC) 110 with a memory array 140. The host SOC 110 includes a memory controller 120 with an ECC encoder/decoder 125 and a PHY block 130. The memory array 140 includes nine 8-bit memory devices 150. An 8-bit ECC can be assigned to each 64-bit data to protect any bit error in both the host SOC 110 and the memory cell array 140. The data can be written to the first eight memory devices 150, and the ECC can be written to the 9th memory device 150.
As seen, the conventional memory configuration incurs additional memory devices cost. It also results in an increased printed circuit board (PCB) area cost by requiring wider memory channel routing and increased memory standby & active power cost due to the additional 9th memory device 150. The additional memory configuration directly impacts performance Memory bandwidth corresponds with how many valid bits are transferred per given amount of time. However, the additional ECC bits, while enhancing reliability, do not themselves have values as data. Thus, the first conventional technique directly impacts the performance of the memory subsystem in that the entire I/O width is not used to transfer useful data.
FIG. 2 illustrates a simplified diagram of the conventional memory subsystem 100, but this time showing only one data (DQ) byte for simplicity. The memory device 150 includes an I/O block 260 and a plurality of memory banks 270. As seen, signal lines, collectively referred to as a link 290, are used to exchange data between the host SOC 110 and the memory device 150. The link 290 includes:                DQ[0:7] lines: DQ byte bidirectional bus for transfer of data between memories and the SOC;        DM line: Data Mask for Write Data;        Data CK line: Clock input to strobe the Write Data;        Read Strobe CK line: Clock output to be aligned with Read Data timing (a clock input to the SOC);        CA[0:n] lines: Command & Address;        CA CK line: Command & Address clock input to fetch CA.        
It should be noted that the DM line may be a Data Mask Inversion (DMI) pin function—either a Data Inversion or Data Mask. The DMI pin function depends on a Mode Register setting. However, in FIG. 2, it is shown as DM line for simplicity.
FIG. 3A illustrates a timing diagram of a conventional mask write operation. The memory controller 120 issues a WRITE command to the memory device 150. After some delay, a byte (8-bits) of data is transferred over each of sixteen burst cycles from the host SOC 110 to the memory device 150. In other words, a 128-bit Write Data (8-bit DQ×burst length 16) is transferred. In FIG. 3A, each of D0-DF represents 8-bits (a byte) of the Write Data DQ[0:7] being transferred in one burst cycle. The Write Data is transferred with some data mask (DM) activities. In this example, a 16-bit DM is used to mask each DQ byte. Conventionally, the Read Strobe clock line is idle since this is a write operation.
FIG. 3B illustrates a timing diagram of a conventional read operation. The memory controller 120 issues a READ command to the memory device 150. After some delay, the memory device 150 responds by sending a 128-bit Read Data (8-bit DQ×burst length 16) to the host SOC 110. Again, each of D0-DF represents a byte of the Read Data DQ[0:7] being transferred in one burst cycle. The Read Strobe clock from the memory device 150 toggles with the Read Data as an input clock to the host SOC 110. The DM line is idle since this is a read operation.
In the second conventional technique, burst lengths are extended to transmit the ECC codes. For example, the burst length can be extended from 16 to 18 (BL16→BL18), and the ECC bits can be transferred between the host SOC 110 and the memory device 150 in burst cycles not used to transfer the DQ bits. This conventional extended data burst length technique also directly impacts performance in that not every cycle is used to transfer useful data.